1. Field of the Invention
A computer system and method of signal transmission via a PCI-Express bus, and more particularly the snooping and blocking processes are introduced to the peripheral devices coupled with the system chips can enter a power-saving mode smoothly.
2. Description of Related Art
Components and the peripheral devices perform in a computer system by the signals transmission thereof. Where a bus, such as peripheral component interconnect (PCI), accelerated graphics port (AGP), is used to transmit digital data stream. Also, a central processing unit (CPU) uses the bus to connect with a South/North Bridge chip or the system memory therein, and a plurality of peripheral devices or the components of the computer system couple to the bus, thereby transmitting signals or data.
Reference is made to FIG. 1, where a computer system couples to a plurality of peripheral devices a, b, c via a PCI bus 16. Under a low power mode supported by the computer system, a PCI cycle command will be executed as a CPU 10 therein receives a power-saving command. While a North Bridge chip 11 and a South Bridge chip 12 transmit the PCI cycle command via the PCI bus 16, the peripheral devices a, b, c will enter the power-saving mode activated by a basic I/O system (BIOS), and even a system memory 13 or a graphic chip 14 will enter the power-saving mode via each proper transmission bus as well. U.S. Pat. No. 6,357,013 discloses a circuit for setting a computer system bus signals to predetermined states in low power mode, but the transmission between the peripheral device and the its bus is still under limitation of the current PCI bus bandwidth. Thus, the South Bridge chip and its coupled peripheral devices need to share merely one pipe with transmission bandwidth of 133 MB/s. If a big-sized file is sent there between, the computer system rate will be degraded since the mentioned data is transmitted in a sequence. If the newly developed device with serial ATA (SATA) interface or a gigabit network with high-transfer transmission rate performs under the PCI standard, the transmission rate will be degraded due to the less bandwidth.
Different from a multi-drop parallel bus technology has been incorporated into the current used PCI bus, PCI-Express further incorporates a switching peer-to-peer sequential transmission technology. In the process of transmission, the physical layer of the PCI-Express bus is composed of a set of single-task lane having a transmit-end and a receive-end. Wherein, each PCI-Express uses its own lane to communicate with the North/South Bridge chip independently rather than use the structure having a common bus. Not only the single-task lane of the PCI-Express can exclude the interference in data transmission, but also each data has the performance privilege of the first priority. Therefore, according to the above-mentioned structure of the PCI-Express standard, rather than the current used PCI bus, PCI-Express will be the main choice for computer system bus.
The PCI-Express standard defines a L2 and L3 power mode for supplying power to the peripheral devices. Where the L2 power mode is defined as both a main power and a reference clock of the computer system are excluded from the power supply except for an auxiliary power. The auxiliary power remains as supplying the lowest power consumption, in which the lowest power mode has a wake-up function for waking the computer system up from a suspend mode. Next, the L3 power mode is defined as both the main power and the reference clock are excluded from the computer system, meanwhile, the auxiliary power is disable either. In the L3 power mode, the computer system can not be waked up until rebooting or resetting.
In prior arts, the L2 or L3 power mode is defined since the power-saving mode of the computer system is initialized after accomplishing the signal transmitting process between the CPU and the South Bridge chip. In the meantime, an OS (operation system) direct power management (OSPM) within the computer system is initializes a preparation for transferring to the power-saving mode since an advanced configuration and power interface (ACPI) installed in the South Bridge chip, so as to drive the peripheral devices using the PCI-Express bus coupled with the South Bridge chip into a specific power-saving mode. In addition, the peripheral devices, such as a graphic card, high-speed network card, coupled with the North Bridge chip don't have any mechanism to enter a power-saving mode in the prior arts.